1. Field of the Invention
The present invention relates to a method of manufacturing a multilayer wiring substrate having a multilayer structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated alternately.
2. Description of Related Art
In association with recent increasing tendency toward higher operation speed and higher functionality of semiconductor integrated circuit devices (IC chips) used as, for example, microprocessors of computers, the number of terminals increases, and the pitch between the terminals tends to become narrower. Generally, a large number of terminals are densely arrayed on the bottom surface of an IC chip and flip-chip-bonded to terminals provided on a motherboard. However, since the terminals of the IC chip differ greatly in pitch from those of the motherboard, difficulty is encountered in bonding the IC chip directly onto the motherboard. Thus, according to an ordinarily employed method, a semiconductor package configured such that the IC chip is mounted on an IC chip mounting wiring substrate is fabricated, and the semiconductor package is mounted on the motherboard.
The IC chip mounting wiring substrate which partially constitutes such a semiconductor package has been has been put to practical use in the form of a multilayer substrate configured such that a build-up layer is formed on the front and back surfaces of a substrate core. The substrate core used in the multilayer wiring substrate is, for example, a resin substrate (glass epoxy substrate or the like) formed by impregnating reinforcement fiber with resin. Through utilization of rigidity of the substrate core, resin insulation layers and conductor layers are laminated alternately on the front and back surfaces of the substrate core, thereby forming respective build-up layers. In the multilayer wiring substrate, the substrate core serves as a reinforcement and is formed very thick as compared with the build-up layers. Also, the substrate core has conductor lines (specifically, through-hole conductors, etc.) extending therethrough for electrical communication between the build-up layers formed on the front and back surfaces.
In recent years, in association with implementation of high operation speeds of semiconductor integrated circuit devices, signal frequencies to be used have become those of a high frequency band. In this case, the conductor lines which extend through the substrate core serve as sources of high inductance, leading to the transmission loss of high-frequency signals and the occurrence of circuitry malfunction and thus hindering implementation of high operation speed. In order to solve this problem, a multilayer wiring substrate having no substrate core is proposed (refer to, for example, Patent Documents 1 and 2). The multilayer wiring substrates described in Patent Documents 1 and 2 do not use a substrate core, which is relatively thick, thereby reducing the overall wiring length. Thus, the transmission loss of high-frequency signals is lowered, whereby a semiconductor integrated circuit device can be operated at high speed.
The multilayer wiring substrate shown in Patent Document 1 is manufactured by the following method. As shown in FIG. 16, there are first prepared a support substrate 81 formed of glass epoxy resin, and a separable copper foil 83 (peelable copper foil) composed of two copper foils 83a and 83b provisionally bonded in a separable manner. The separable copper foil 83 is then fixed onto the support substrate 81 via an adhesive resin layer 82. Subsequently, as shown in FIG. 17, a laminate structure 87 (build-up layer) is obtained through performance of a lamination step (build-up step) of laminating a plurality of resin insulation layers 85 and a plurality of conductor layer 86 alternately on the separable copper foil 83. Furthermore, the laminate structure 87 is cut at positions outside a product area (positions indicated by broken lines in FIG. 17), whereby the separation interface of the separable copper foil 83 (the interface between the two copper foils 83a and 83b) is exposed. After that, through separation at the separation interface of the separable copper foil 83, the laminate structure 87 is separated from the support substrate 81, whereby a coreless, thin multilayer wiring substrate is obtained.
The multilayer wiring substrate shown in Patent Document 2 is manufactured by the method shown in FIG. 18. First, there are prepared a support substrate body 91 formed of a resin substrate (pre-preg) in a semi-cured state (B-stage), a ground layer 92 formed of copper foil, and a support metal layer 93 which is formed of copper foil and which is larger in outer shape than the ground layer 92. The ground layer 92 and the support metal layer 93 are then placed on the support substrate body 91. Heat and pressure are applied to them in a vacuum atmosphere, whereby the ground layer 92 and a portion of the support metal layer 93 extending outward from the ground layer 92 are bonded onto the support substrate body 91, whereby a support substrate 94 is formed. Subsequently, as shown in FIG. 19, a laminate structure 97 is obtained through performance of a lamination step of laminating a plurality of resin insulation layers 95 and a plurality of conductor layer 96 alternately on the support metal layer 93 of the support substrate 94. Furthermore, the laminate structure 97 is cut at positions outside a product area (positions indicated by broken lines in FIG. 19), whereby the interface between the support metal layer 93 and the ground layer 92, which are formed of two copper foils, is exposed. After that, at the interface between the support metal layer 93 and the ground layer 92, the laminate structure 97 is separated from the support substrate 94, whereby a coreless, thin multilayer wiring substrate is obtained.